1. Field of the Invention
The present invention relates to improvements in multi-phase synchronous buck converters, and in particular, to such devices having improved techniques for output current sensing, for current sharing between modules, and improved transient performance during rapid load changes. The invention is described and shown in the context of a multi-chip module (MCM) implementation, but the improvements disclosed are applicable to discrete component implementations as well.
2. Relevant Art
An MCM is an electronic package which includes multiple integrated circuits (ICs) formed on a common substrate with multiple interconnecting layers, separated by insulating material. The entire module is encapsulated, but not the individual ICs.
MCMs offer several important benefits over circuits formed of separate chips mounted on conventional printed circuit boards. These include increased wiring and component densities, and lower cost. Also, the compact architecture of MCMs can result in shorter signal transmission times and reduced parasitic impedance, which in turn, improves high-speed switching efficiency. Also, including passive components inside MCM makes the MCM more testable as a complete power supply with consequent improved reliability.
MCM packaging is suitable for a wide variety of applications, including multi-phase synchronous buck converters. A synchronous buck converter is a switched D.C. power supply which receives a D.C. (or a rectified A.C.) input and produces a regulated low-voltage output with high output current capacity. Buck converters are particularly useful as power supplies for microprocessor operated devices, and a wide range of other digital circuit applications.
The basic configuration of a synchronous buck converter is illustrated in FIG. 1. The circuit, generally denoted at 100, includes a series switch 102 which is typically a power MOSFET or the like, with its source-drain path connected between an input terminal 104 and a first signal node 106, a shunt switch 108, also typically a power MOSFET or the like, and an output circuit comprised of an series inductor 112 and a shunt capacitor 114 connected to inductor 112 at a signal output node 116 and to ground 110. A shunt diode such a Shottky diode 118 may also be provided in parallel with MOSFET 108 if desired to provide conduction during the deadtimes of 108 to reduce the diode reverse recovery loss associated with the internal body diode of MOSFET 108. A separate diode 118 is not required if the higher switching loss is deemed preferable to the added cost of the external Schottky.
A D.C. input voltage VIN is provided between input terminal 104 and ground 110 across an input capacitor 111, and an output voltage VOUT which is less than VIN is provided to a load 124 connected between signal output node 116 and ground 110.
Control of the output voltage is provided by selectively varying the on-off duty cycles of MOSFETS 102 and 108. This is done by a gate control logic or driver circuit 120 connected to the gate terminals of the MOSFETS, and driven by a pulse width modulation circuit 124 comprised of a PWM generator 124 which compares a ramp signal of the required switching frequency and having fixed maximum (peak) and minimum (valley) values with a signal provided by an error amplifier 126. The latter provides an output signal VE based on the difference between the actual output voltage represented by a feedback signal VFB on signal line 128 and a desired output voltage signal VREF provided at a second input terminal 130.
In operation, with MOSFET 102 on and MOSFET 108 off, the voltage across inductor 112 is equal to VIN−VOUT, and the resulting current charges capacitor 114. To maintain substantially constant voltage across capacitor 114, a predetermined value of VE operates PWM circuit 124 and gate driver 120 to switch MOSFET 102 off, and MOSFET 108 on. The very low source-drain resistance of MOSFET 108 when it is conducting maintains a circuit to sustain the current flow through inductor 112. This, in turn, allows capacitor 114 to charge, and after several on-off cycles for the MOSFETS, a steady-state output voltage is achieved. The operation of the circuit shown in FIG. 1 is well known to persons skilled in the art, and a further description will be omitted in the interest of brevity.
Where output currents exceeding the capacity of MOSFETS 102 and 108 are required, a multi-phase buck converter can be employed, as illustrated schematically by circuit 200 shown in FIG. 2. Here, N synchronous buck converters stages 202A-202N are connected between an input node 108 and a common ground 210 and with their outputs feeding an output node 212. Thus, each stage contributes a portion of the required current demand.
Converter stage 202A includes an input capacitor 203, a MOSFET pair 204, an a shunt Shottky diode 205, an output inductor 206, an output capacitor 214, and a gate drive circuit 216. The other converter stages are similarly constructed.
A master PWM controller 218 generates N interleaved or out of phase PWM signals with 360°/N phase delay between phases. Master controller 218 may be constructed in any suitable or desired manner, and may be comprised, for example, of an adjustable frequency master clock 220 operating at a frequency FM=N·fSW, where N is the number of phases, and fSW is the predetermined switching frequency for the MOSFETS, a programmable counter 222 to generate a pulse train at frequency fSW, a succession of N series-connected PWM circuits 224A-224N, and an error amplifier 226. The latter provides a common input to trigger the PWN circuits whereby a series of drive signals PWM-1 through PWM-N are provided as inputs to gate driver 206 in converter stages 202A-202N.
The drive signals are separated by a phase delay of 360/N, as shown in FIG. 3, which illustrates the timing of the synchronization signals for a five-phase converter with a 5 MHz clock frequency, and a 1 MHz switching frequency. From this, it will be seen that the five converter stages operate in a staggered fashion during five successive 1 MHz switching cycles, each interleaved by (⅕)*10−6 sec. As multi-phase synchronous buck converters are well known to those skilled in the art, further details concerning the arrangement shown in FIG. 2 are omitted (as in the case of FIG. 1) in the interest of brevity.
There are, however, certain respects in which further improvements to existing designs for synchronous buck converters would be desirable. Among these are:                (a) Improved ways of generating the current feedback signal for input to the PWM controller. The output voltage and the current sharing in the individual converter stages of a multi-phase converter are controlled by the switching duty cycle for the MOSFETS. Since high output currents favor “lossless” type sensing, the current feedback signal is conventionally generated by a sample and hold circuit 400 such as illustrated in FIG. 4. Here, the voltage across the RDS-ON of shunt MOSFET 402 is sampled once during each MOSFET switching cycle. Sample and hold circuit 400 includes transistors 404 and 406 (shown for simplicity as on-off switches) and a capacitor 408.        
Alternatively, if the VIN to VOUT ratio is such that the series FET has large duty cycle, the voltage across the RDS-ON of the series MOSFET rather than the shunt MOSFET can be sampled.
Either way, however, due the small value typical of RDS-ON, however, the sampled voltage signal must be amplified by amplifier 410.
There are several drawbacks to this approach. For one thing, amplifier 410 needs to have a high bandwidth and high slew rate to accurately sample the voltage across the RDS-ON of shunt MOSFET 402. Also, the output of amplifier 410 takes time to settle which limits its high frequency response. Further, there is inherently a large current ripple content in the inductor current, and it is reflected in a ripple voltage across RDS-ON. Depending on the timing of sampling, the sampled signal may not reflect the D.C. output current, so the inductor ripple current magnitude and sampling timing can affect current sensing error.                (b) Current sharing among Converter Stages. MCM construction can advantageously be used for multi-phase synchronous buck converters. MCMs can be provided for each converter stage, (including, if desired, the input and output capacitors and the series inductor in the converter stage module), and also for the master PWM controller 218 as indicated by the topology of FIG. 2. Conventionally, a separate controller is provided to control current sharing, or the function is incorporated in the master PWM controller. Both approaches are complex and do not lend themselves well to scaling the number of phases. Also, due to the large output currents, lossless sensing is normally employed, with the consequent drawbacks described above. Moreover, the selection of current sense gain is not on a stage-by-stage basis. This leads to inaccurate current sharing because in MCM construction, the RDS-ON of the shunt MOSFET can vary between modules, and also with temperature and gate voltage.        (c) Variations in Conduction Losses between Modules. Module-to-module variation of RDS-ON also can cause unbalanced conduction losses in the shunt MOSFET. More particularly, in a multi-phase power supply, the total output current deliverable is determined by the weakest, i.e., hottest running module. To maximize the output current capability, the weakest module should be called on to deliver the least current, and therefore power sharing is even more important than current sharing.        
Conventional designs do not provide effective power sharing. To understand this, with reference again to FIG. 2, consider a two-stage converter, i.e., N=2. Assume also the following:RDS-ONof shunt MOSFET # (in module 202-1)=0.005ΩRDS-ONof shunt MOSFET (in module 202-2)=0.006ΩOutput current IOUT=20 AVIN=12.0VVOUT=1.0V
Using conventional MOSFET RDS-ON current sensing, and considering the two phase modules in parallel, the current in each phase will actually be determined by the effective parallel resistance. In other words, the current in module 202-1 will actually be 20*6/(5+6)=10.9 A, and the current in module 202-2 will actually be 20*5/(5+6)=9.1 A. Thus, the respective I2 R losses will be 0.59 W and 0.5 W.
Even on the assumption of perfect current sharing, i.e., that each module may somehow be designed to contribute exactly 10.0 A of the 20 A output, the I2 R loss in module 202-1 will be 0.5 W, and 0.6 W in module 202-2. As may be understood, the situation can be much worse with greater RDS-ON imbalance.                (d) Undesirable transient behavior during load changes. When there are rapid load transitions, asymmetrical output voltage overshoot and undershoot are observed due to the large ratio of VIN and VOUT. The output voltage overshoot with load step-down is usually greater than the undershoot with load step-up. To prevent voltage overshoot, large and costly output capacitors have conventionally been used.        
It may thus be seen that there are still problems with multi-phase synchronous buck converters according to the state of the art. The present invention seeks to alleviate some of these problems.